The present invention relates to a signal delay compensating circuit for correcting a phase difference between two signals due to a difference in the delay time between a clock signal and a data signal at the time of effecting the transmission and reception of data in synchronism with the clock signal or the like.
In digital circuits for inputting and outputting data in synchronism with a clock signal or the like, the frequency of the clock signal conventionally tends to be high owing to a demand for higher data processing speed. In addition, circuits and the like which share the same clock signals have come to increase as semiconductor integrated circuits and systems using them have come to adopt multifunctions. The load of clock signal lines has also increased in conjunction with this trend. Accordingly, in a circuit for handling a high-frequency clock signal, the effect of an increase in the load causes a delay of the clock signal, and lacks a balance with the delay of data, with the result that there is a possibility that the phase difference brings about a serious problem in the operation of the circuit. To cope with such a problem, a proposal has been made in which a latch circuit for synchronizing the semiconductor circuit device from an external circuit is provided in an input/output buffer portion of the semiconductor device (e.g., refer to JP-A-64-23549).
FIGS. 10 and 11 show a conventional circuit configuration and voltage waveforms of respective portions of the circuit.
This circuit is comprised of a semiconductor circuit device 100 and a receiving circuit 4. The semiconductor circuit device 100 is configured by a clock-signal generating circuit 1, a data processing circuit 2, a latch circuit 3, output buffer circuits 6a and 6b, a data input terminal 7, a clock output terminal 8, and a data output terminal 9. The clock-signal generating circuit 1 is a circuit for generating a master clock signal serving as a reference for the circuit operation. The data processing circuit 2 processes a data signal inputted to the data input terminal 7 by a predetermined procedure, and outputs the data signal to the latch circuit 3 in synchronism with the master clock signal.
The latch circuit 3 temporarily stores the data signal outputted from the data processing circuit 2, and outputs the data signal to the receiving circuit 4 via the data output terminal 8 in synchronism with the master clock signal. The receiving circuit 4 is a circuit for fetching the input data signal in synchronism with the master clock signal. A load 5 is one which is based on an external environment such as the stray capacitance and the impedance of a wiring pattern and the like.
In such a conventional circuit, even if processing for matching the phases of the master clock signal (see the signal A in FIG. 11) and the output data signal (see the signal C in FIG. 11) is effected on the output side of the data signal, the master clock signal inputted to the receiving circuit 4 is delayed (see the signals B and D in FIG. 11) due to the effect of the load based on the external environment. As a result, the phase relationship between the output data signal and the master clock signal on the receiving circuit 4 side, i.e., the amount of relative delay between the two signals, changes.
Such a situation results in cutting a margin in transmission on the receiving circuit 4 side (e.g., setup time and hold time), which leads to instability in the transmission of the data signal and a transmission error of the data signal. In particular, in a system in which data is transmitted with the same phase as that of the master clock signal, the output timing of the data signal is slightly delayed as compared to the master clock signal on the precondition that transmission processing of the data signal is effected with respect to a clock signal. Therefore, if an attempt is made to secure the setup time on the receiving circuit 4 side, the effect of the external load cannot be ignored.